The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) requires metallic wiring that connects individual devices in a semiconductor chip, to one another. One method of creating this wiring network on such small scale is the dual damascene (DD) process schematically shown in FIG. 1. In the standard DD process, an interlayer dielectric (ILD), shown as two layers 110, 120 is coated on the substrate 100, FIG. 1a. The via level dielectric 110 and the line level dielectric 120 are shown separately for clarity of the process flow description. In general, these two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer 130 is optionally employed to facilitate etch selectivity and to serve as a polish stop as will be seen later. The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip, and the via features which connect lines in different levels together. Historically, both layers are made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica film deposited by plasma enhanced chemical vapor deposition (PECVD).
In the dual damascene process, the position of the lines 150 and the vias 170 are defined lithographically in photoresist layers, 140, depicted in FIGS. 1b and 1d, and transferred into the hard mask and ILD layers using reactive ion etching processes. The process sequence shown in FIG. 1 is called a Line-first approach because the trench 160 which will house the line feature is etched first, see FIG. 1c. After the trench formation, lithography is used to define a via pattern 170 in the photoresist layer 140 which is transferred into the dielectric material to generate a via opening 180, FIG. 1d. The dual damascene trench and via structure 190 is shown in FIG. 1e after the photoresist has been stripped. This structure 190 is coated with a conducting liner material or material stack 200 that serves to protect the conductor metal lines and vias and serve as an adhesion layer between the conductor and the ILD. This recess is then filled with a conducting fill material 210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper although other methods such as chemical vapor deposition (CVD) and other materials such as Al or Au can also be used. The fill and liner materials are then chemically-mechanically polished (CMP) to be coplanar with the surface of the hard mask and the structure at this stage is shown in FIG. 1f. A capping material 220 is deposited over the metal or as a blanket film, as is depicted in FIG. 1g to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional ILD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material 220. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are defined to form a conductor in-lay within an insulator by a single polish step, this process is designated a dual damascene process.
As with any circuit, semiconductor chips are prone to signal propagation delays which depend on the product of the line resistance, R, and the interconnect capacitance, C. In order to improve the performance of semiconductor chips, manufacturers have reduced the resistivity of the metal used in fabrication by replacing aluminum wiring by copper. By moving to lower dielectric constant (k) materials, manufacturers have also begun to reduce the capacitance, C, in the circuit. The common terminology used to describe the dielectric films is to classify them as standard k (4.5<k<10), low k (k<3.0), ultra low k (2.0<k<2.5) and extreme low k (1.5<k<2.0). Ultra low k and extreme low k dielectrics generally tend to be porous with intentionally engineered voids in their structure. Since the lowest dielectric constant possible is defined by air or vacuum (kvac=1), many have developed means to produce voids in the dielectric. When the void volume extends and occupies substantial contiguous regions of the gaps between the lines one achieves an interconnect structure wherein the lines are nominally separated by air or vacuum as the ILD material. In the following descriptions the term air bridge is used to describe such an interconnect structure to distinguish it from structures wherein the ILD is porous with void volume dispersed within a nominally contiguous solid dielectric.
One prior art approach to air bridge construction is shown in FIG. 2. In this process, a low-k structure is constructed after metal deposition steps to form the interconnects, as for example by a DD process. For the purpose of reference, these types of processes are designated in the present application as Metal-then-Air Bridge (MAB) approaches consistent with the process sequence used. Most processes that follow this approach begin with the standard DD fabrication sequence. Thus the FIGS. 2a, 2b, 2c and 2d replicate the process flow in FIGS. 1a, 1b, 1c, 1d, 1e and 1f, albeit in an abbreviated manner. Thus, for example, the structure shown in FIG. 2d is identical to the DD structure shown in FIG. 1f. After the standard DD structure is thus completed, openings are defined lithographically in all or a selected subset of the gaps between the interconnect line features and etched into the top surface of the capping layer 220 and the hardmask layer 130. These openings are parallel to the line edges and are then used to remove the underlying ILD to create inter-metal line cavities 230 running the length of the lines as shown in FIG. 2e. Chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD) of a dielectric film 240 such as silicon oxide is then performed to form a conformal coating on the inside of the cavity as well as to cause a pinch point near the cavity entrance thus, creating the air-bridge structure 250 shown in FIG. 2f. Additional levels are then fabricated in the same manner above the air bridge level as shown in FIG. 2g. 
These MAB approaches require extensive knowledge and manipulation of the CVD or PECVD processes used to deposit the pinch off dielectric 240 and will pose significant difficulties for interconnects with varying line pitch. For example, wider inter-line gaps will require much thicker film deposition for pinch off than the narrower ones, thereby requiring compromises. Further, as the line widths and spacings decrease in future technology generations, the fraction of the gap between the lines occupied by the conformal sidewall coating can become large thus increasing the inter-line capacitance. Since the deposition is performed after the initial structure is constructed, depending on the aspect ratio of the gaps, some portions of the sidewall may not be covered which leads to reliability issues of exposed metal lines or metal vias. Further, most MAB processes require a layer by layer air bridge formation. Therefore, the integrity of the air-bridge cavity may be breached when subsequent processes to build upper interconnect layers are carried out. For example, referring to FIG. 2g, if the via portion 310 of an upper level 290 is not perfectly aligned to an underlying metal line 210 of the first level, the via etch may open through the bridge into the air gap below. In this case when METALLIZATION of the upper level is performed, the air gap below will be filled with metal causing electrical shorts between the lines.
It is therefore clear that an alternate approach that will circumvent the above detailed limitations of the MAB approaches is required in order to fabricate reliable multilevel air bridge structures.